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MC10231 High Speed Dual Type D Master-Slave Flip-Flop
The MC10231 is a dual master-slave type D flip-flop. Asynchronous Set (S) and Reset (R) override Clock (CC) and Clock Enable (CE) inputs. Each flip-flop may be clocked separately by holding the common clock in the low state and using the enable inputs for the clocking function. If the common clock is to be used to clock the flip-flop, the Clock Enable inputs must be in the low state. In this case, the enable inputs perform the function of controlling the common clock. The output states of the flip-flop change on the positive transition of the clock. A change in the information present at the data (D) input will not affect the output information at any other time due to master-slave construction. * PD = 270 mW typ/pkg (No Load) * tpd = 2 ns typ * tTog = 225 MHz typ * tr, tf = 2.0 ns typ (20%-80%)
LOGIC DIAGRAM
S1 5 D1 7 CE1 6 Q1 Q1 R1 4 CC 9 R2 13 Q2 CE2 11 D2 10 S2 12 Q2 2 3 VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 15 14 A WL YY WW
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16 CDIP-16 L SUFFIX CASE 620 1 16 PDIP-16 P SUFFIX CASE 648 1 1 PLCC-20 FN SUFFIX CASE 775 10231 AWLYYWW MC10231P AWLYYWW MC10231L AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week
DIP PIN ASSIGNMENT
VCC1 Q1 Q1 R1 S1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC2 Q2 Q2 R2 S2 CE2 D2 CC
CLOCKED TRUTH TABLE
C L H H D X L H Qn+1 Qn L H
R-S TRUTH TABLE
R L L H H S L H L H Qn+1 Qn H L N.D.
CE1 D1 VEE
C = CE + CC. A clock H is a clock transition from a low to a high state.
N.D. = Not Defined
Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D).
ORDERING INFORMATION
Device MC10231L MC10231P MC10231FN Package CDIP-16 PDIP-16 PLCC-20 Shipping 25 Units / Rail 25 Units / Rail 46 Units / Rail
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 6
Publication Order Number: MC10231/D
MC10231
ELECTRICAL CHARACTERISTICS
Test Limits Pin Under Test 8 4 5 6 7 9 4, 5* 6, 7, 9* 2 2[ 3 3[ 2 2[ 3 3[ -1.060 -1.060 -1.890 -1.890 -1.080 -1.080 -1.655 -1.655 -0.890 -0.890 -1.675 -1.675 -30C Min Max 72 650 650 350 350 460 0.5 0.5 -0.960 -0.960 -1.850 -1.850 -0.980 -0.980 -1.630 -1.630 -0.810 -0.810 -1.650 -1.650 -0.890 -0.890 -1.825 -1.825 -0.910 -0.910 -1.595 -1.595 -0.700 -0.700 -1.615 -1.615 Min +25C Typ 52 Max 65 410 410 220 220 290 Min +85C Max 72 410 410 220 220 290 Unit mAdc Adc
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Logic 1 Logic 0 Logic 1 Logic 0 VOH VOL VOHA VOLA
Adc Vdc Vdc Vdc Vdc ns
Switching Times (50 Load) Clock Input Propagation Delay Rise Time Fall Time Set Input Propagation Delay t5+2+ t12+15+ t5+3- t12+14- 2 15 3 14 1.1 1.1 1.1 1.1 3.4 3.4 3.4 3.4 1.1 1.1 1.1 1.1 2.0 2.0 2.0 2.0 3.3 3.3 3.3 3.3 1.2 1.2 1.2 1.2 3.7 3.7 3.7 3.7 (20 to 80%) (20 to 80%) t9+2- t6+2+ t2+ t2- 2 2 2 2 1.5 1.5 0.9 0.9 3.4 3.4 3.3 3.3 1.5 1.5 1.0 1.0 2.0 2.0 1.3 1.3 3.3 3.3 3.1 3.1 1.6 1.6 1.0 1.0 3.7 3.7 3.6 3.6
ns
Reset Input Propagation Delay t4+2- t13+15- t4+3- t13+14+ tsetup thold 2 15 3 14 7 7 1.1 1.1 1.1 1.1 1.5 0.9 3.4 3.4 3.4 3.4 1.1 1.1 1.1 1.1 1.0 0.75 200 225 2.0 2.0 2.0 2.0 3.3 3.3 3.3 3.3 1.2 1.2 1.2 1.2 1.5 0.9 200 VIHmax VILmin 3.7 3.7 3.7 3.7
ns
Setup Time Hold Time
ns ns MHz
Toggle Frequency (Max) ftog 2 200 * Individually test each input; apply VILmin to pin under test.
[ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
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MC10231
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts) @ Test Temperature -30C +25C +85C Pin Under Test 8 4 5 6 7 9 4, 5* 6, 7, 9* 2 2[ 3 3[ 2 2[ 3 3[ +1.11Vdc Propagation Delay Rise Time Fall Time Set Input Propagation Delay t5+2+ t12+15+ t5+3- t12+14- 2 15 3 14 6 9 5 12 5 12 2 15 3 14 8 8 8 8 1, 16 1, 16 1, 16 1, 16 (20 to 80%) (20 to 80%) t9+2- t6+2+ t2+ t2- 2 2 2 2 7 7 5 7 5 7 5 7 5 7 Pulse In 9 6 9 9 9 9 Pulse Out 2 2 2 2 4 5 6 7 9 * * VIHmax -0.890 -0.810 -0.700 VILmin -1.890 -1.850 -1.825 VIHAmin -1.205 -1.105 -1.035 VILAmax -1.500 -1.475 -1.440 VEE -5.2 -5.2 -5.2 (VCC) Gnd 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 +2.0 V 1, 16 1, 16 1, 16 1, 16
TEST VOLTAGE APPLIED TO PINS LISTED BELOW VIHmax VILmin VIHAmin VILAmax VEE 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -3.2 V 8 8 8 8
Characteristic Power Supply Drain Current Input Current
Symbol IE IinH
IinL Output Voltage Output Voltage Threshold Voltage Threshold Voltage Switching Times Clock Input Logic 1 Logic 0 Logic 1 Logic 0 (50 Load) VOH VOL VOHA VOLA
Reset Input Propagation Delay t4+2- t13+15- t4+3- t13+14+ tsetup thold 2 15 3 14 7 7 6 9 4 13 4 13 6, 7 6, 7 6 2 15 3 14 2 2 2 VIHmax 8 8 8 8 8 8 8 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16 1, 16
Setup Time Hold Time
Toggle Frequency (Max) ftog 2 ** * Individually test each input applying VIH or VIL to input under test.
[ Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VILmin Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to -2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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MC10231
PACKAGE DIMENSIONS
PLCC-20 FN SUFFIX PLASTIC PLCC PACKAGE CASE 775-02 ISSUE C
B -N- Y BRK D -L- -M- W D X V A Z R 0.007 (0.180) M T L-M
S
0.007 (0.180) M T L-M U
S
N
S S
0.007 (0.180) M T L-M
N
S
Z
20
1
G1
0.010 (0.250)
S
T L-M
S
N
S
VIEW D-D 0.007 (0.180) M T L-M
S
N N
S
H
0.007 (0.180) M T L-M
S
N
S
S
K1 K
C
E 0.004 (0.100) G G1 0.010 (0.250) S T L-M J -T-
SEATING PLANE
F VIEW S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
0.007 (0.180) M T L-M
S
N
S
VIEW S
S
N
S
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.385 0.395 0.385 0.395 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.350 0.356 0.350 0.356 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10 _ 0.310 0.330 0.040 ---
MILLIMETERS MIN MAX 9.78 10.03 9.78 10.03 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 8.89 9.04 8.89 9.04 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10 _ 7.88 8.38 1.02 ---
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MC10231
PACKAGE DIMENSIONS
CDIP-16 L SUFFIX CERAMIC DIP PACKAGE CASE 620-10 ISSUE T
-A-
16 9
-B-
1 8
C
L
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G H K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 --- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 --- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01
-T-
SEATING PLANE
N E F D G
16 PL
K M J
16 PL
0.25 (0.010)
M
M
TB
S
0.25 (0.010)
TA
S
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
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MC10231
Notes
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MC10231
Notes
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MC10231
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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MC10231/D

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